-- JaredSmolens - 06 Jul 2007

Introduction

This section explains how to integrate a new stall signal into the thread scheduler for the OpenSPARC T1. Stall signals are necessary to pause the execution of an active (schedulable) thread during situations such as an I-cache miss, retirement queues fill or a pipeline resource becomes busy.

Background

The OpenSPARC T1's instruction selection stage chooses ready instructions from a pool of active threads (see the Microarchitecture document for more information on the thread scheduler states). We are primarily interested in transitioning thread from Ready and Run states to the Wait state (Figure 2-10).

The signal-level interface which must be provided comprises two signals: a thread stall signal and a thread ready signal, called af_stall and af_resume in this section. The thread stall signal is asserted whenver a thread should be first placed in the Wait state. The thread ready signal is asserted whenever the thread can be started again. The signals should not be asserted simulataneously, however it is acceptable for neither to be asserted in a given cycle and the values need only be asserted for a single clock. This section assumes that these signals contain one bit per thread (e.g, four bits [3:0]), although a single signal that affects all threads can be trivially substituted.

With these signals, you will generate two signals: a wait-mask (wm) signal and wait completion signal. These will be combined with existing wait-masks and the completion signal such that any wait-mask can stall a thread, but the thread can only resume when the wait-masks are clear and the operation blocking execution has completed.

This logic will closely follow that used for the existing instruction miss (imiss) logic, however because the different stall causes may become ready independently and the thread can only start when all wait-masks have been reset, you should create a new wait-mask instead of piggybacking on an existing one.

Two modules will modified:

Hierarchical Name	Description	Module	Filename
ifu.swl	switch logic unit	sparc_ifu_swl	design/sys/iop/sparc/ifu/rtl/sparc_ifu_swl.v
ifu.swl.compl	stall completion logic	sparc_ifu_thrcmpl	design/sys/iop/sparc/ifu/rtl/sparc_ifu_thrcmpl.v

Implementation

First, add the stall and thread ready signals to both the thread switch logic and completion logic modules.

The wait-mask logic is generated with logic to "set" and "reset" the wait-mask value for each thread. The wait-mask is set whenever your stall signal is first asserted and is maintained until reset by the af_resume signal. The signal wm_fpnt is the current wait-mask for this resource.

   wire [3:0] wmf_next;

   assign  wmf_nxt  = af_stall | // set
                      ( wm_fpnt & ~af_resume ); // reset

Within the thread completion logic, add a four-bit flop to store the new wait-mask (wm_fpnt in this example):

   dffr #(4) wmf_ff(.din ( wmf_nxt ),
                    .q ( wm_fpnt ),
                    .clk ( clk ),
                    .rst ( reset ),
                    .se ( se ), .si(), .so() );

At the end of the module, add the following logic to the completion signal:

   assign completion = ((imiss_thrrdy | ~wm_imiss) &
                        (other_thrrdy | ~wm_other) &
                        (stb_retry | ~wm_stbwait) &
                        (af_resume | ~wm_fpnt) &
                        (wm_imiss | wm_other | wm_stbwait | wm_fpnt));

The completion signal allows the thread to start running again. This will only happen when all wait-masks are clear and at least one resume signal has been asserted.

Finally, the new wait-mask signal must be routed out of the thread completion unit and into the parent switch logic module. The individual signals are then combined into "start_thread" and "thaw_thread" signals which control the scheduler FSM. The necessary additions are:

   assign start_thread = resum_thread & (~wm_imiss | ifq_dtu_thrrdy) & 
                                          (~wm_stbwait | stb_retry) & 
                                          (~wm_fpnt | af_resume);

   assign thaw_thread = resum_thread & (wm_imiss & ~ifq_dtu_thrrdy |
                                        wm_stbwait & ~stb_retry    |
                                        wm_fpnt    & ~af_resume);

Updating the Monitor

This is sufficient for modifying the core logic to support an additional stall signal. Howver, a thread scheduler monitor which is used for verification and debugging must also be modified to be aware of the new stall signal. Note that this monitor can be disabled with the -sim_run_args=+turn_off_thread_monitor command line switch to sims.

Edit the files verif/env/cmp/monitor.v and verif/env/cmp/thrfsm_mon.v. The first file instantiates various microrchitectural monitors and needs to route the wait-mask signal (e.g., wm_fpnt) into the thrfsm monitor. From there, simply copy the logic used for wm_imiss, replacing wm_imiss with wm_fpnt on the new lines.