This chapter is starting with resources and commentary on EDA tools as well as additional pointers to IP needed for the implementation of OpenSPARC RTL.

If You Are New to EDA, please refer back to the OpenSPARC web-site over here: http://www.opensparc.net/eda.html

However, if you have done a thing or two using CAD/EDA tools, perhaps there's something I can add to explore further

• Let's take the prototyping aspects. While some of you may want to use FPGA, there are vendors (see www.dac.com
  for some of the FPGA vendors) who are coming up with 'stackable' boards of high density, high capacity
  FPGAs. With such boards, you can implement very large designs including system components/ASICs. One such vendor
  claimed capacities of 'as large a system as you want' when talking to their representative at an expo.
  
• If, however, you have decided to implement it into a foundry (a chip fabrication facility) provided ASIC or SoC? , then you
  have even more options to consider. Usually, these foundaries will provide design services, where they can provide foundry specific
  services using their own certified EDA tool chain, including RTL to logic implementation, or logic to physical implementation
  or even packaging, and providing fully tested parts. Almost every large foundry in the world has these
  'certified' tool-chain and tool usage methodology that work with the foundry specific process. These often include
  pre-characterized and pre-silicon verified standard libraries, memory compilers and even standardized IOs.
  Some components are also available as "hard IP", for example standard IO drivers for memories or high speed
  serial ports.
  
• Of course, there's always the last, most customised option, Customer-Owned-Tooling, or COTs for short,
  where you, as a designer team, buy your own implementation tools, except those for mask-making and fabrication.
  As the process features get smaller than the wavelengths of light, more and more fabless semiconductor
  design houses, who are designing chips at the high-end of the spectrum for a given process,
  tend to own their own EDA tools. Including, of course, Sun, when designing OpenSPARC T1.
  
  • Along with the sheer complexity of nanometer technologies the tooling techniques reache new thresholds.
    Tools used for 180 nanometer technology would just fail at 65 nanometer.
    
  • Costs scale up significantly, specially with the industry standard commercial tools. After all, who can
    do a design of 100s of millions of transistors without EDA tools?
    Aah, won't this be a prime ground for open source? I believe that OpenSPARC would help trigger
    more and more open sourcing of EDA tools as the community collaboration picks up.
    
  • Certainly, almost all large commercial organizations as well as universities already have some business
    arrangements with the top vendors, but more often then not, there is limited usage available. And, given
    the pace of process technology changes, EDA tools start to get obsolete quickly.
    
  • Take, for example, logic synthesis. There are probably only 3 or 4 vendors who have credible, high
    capacity and silicon-proven synthesis tools. When combined with physical synthesis (logic synthesis
    that is also aware of physical constraints like distances, routing congestions, etc.), the solutions are
    even fewer. Add to this any features that help to manage the complexity of processes that have
    large variability in the physical structures (even within one chip), and you'll need a whole new class
    of capabilities, generally referred to as 'DFx' or Design for Manufacturing/Yield/Variability/etc.
    

-- AmanJoshi? - 11 Sep 2006