This chapter defines concepts and terminology common to all implementations of UltraSPARC? Architecture.

aliased
Said of each of two virtual addresses that refer to the same underlying memory location.

address space identifier (ASI)
An 8-bit value that identifies an address space. For each instruction or data access, the integer unit appends an ASI to the address. See also implicit ASI.

application program
A program executed with the virtual processor in nonprivileged mode. Note: Statements made in this specification regarding application programs may not be applicable to programs (for example, debuggers) that have access to privileged virtual processor state (for example, as stored in a memory-image dump).

ASI
Address space identifier.

ASR
Ancillary State register.

available (virtual processor)
A virtual processor that is physically present and functional, that can be enabled and used.

big-endian
An addressing convention. Within a multiple-byte integer, the byte with the smallest address is the most significant; a byte’s significance decreases as its address increases.

BLD
"Legacy" abbreviation for block load (now LDBLOCKF).

BST
"Legacy" abbreviation for block store (now STBLOCKF).

bypass ASI
An ASI that refers to memory space and for which the MMU does not perform address translation (that is, memory is accessed using a direct physical address).

byte
Eight consecutive bits of data, aligned on an 8-bit boundary.

clean window
A register window in which all of the registers contain 0, a valid address from the current address space, or valid data from the current address space.

CMP
Chip-level multiprocessor. A processor cluster containing more than one processor core. coherence
A set of protocols guaranteeing that all memory accesses are globally visible to all caches on a shared-memory bus.

completed (memory operation)
Said of a memory transaction when an idealized memory has executed the transaction with respect to all processors. A load is considered completed when no subsequent memory transaction can affect the value returned by the load. A store is considered completed when no subsequent load can return the value that was overwritten by the store.

consistency
See coherence.

context
A set of translations that supports a particular address space. See also Memory Management Unit (MMU).

copyback
The process of copying back a dirty (“owned”) cache line present in the cache, in response to snoop request from another processor. CPI Cycles per instruction. The number of clock cycles it takes to execute an instruction.

core
In a UltraSPARC? Architecture processor, the term core may be used to refer to either a virtual processor or a physical processor core.

cross-call
An interprocessor call in a multiprocessor system.

CTI
Abbreviation for control-transfer instruction.

current window
The block of 24 R registers that is currently in use. The Current Window Pointer (CWP) register points to the current window.

data access (instruction)
A load, store, load-store, or FLUSH instruction.

DCTI
Delayed control transfer instruction.

demap
To invalidate a mapping in the MMU.

denormalized number
A nonzero floating-point number, the exponent of which has a value of zero. Amore complete definition is provided in IEEE Standard 754-1985.

deprecated
The term applied to an architectural feature (such as an instruction or register) for which a UltraSPARC? Architecture implementation provides support only for compatibility with previous versions of the architecture. Use of a deprecated feature must generate correct results but may compromise software performance. Deprecated features should not be used in new UltraSPARC? Architecture software and may not be supported in future versions of the architecture.

disable (core)
The process of removing a virtual processor from operation, which will normally complete during the next system or power-on reset. disabled (core) A virtual processor that is out of operation (not executing instructions and not participating in cache coherency).

dispatch
To send a previously fetched instruction to one or more functional units for execution. Typically, the instruction is dispatched from a reservation station or other buffer of instructions waiting to be executed. (Other conventions for this term exist, but the this specification attempts to use dispatch consistently as defined here. See also issued.

doublet
Two bytes (16 bits) of data.

doubleword
An 8-byte datum. Note: The definition of this term is architecture dependent and may differ from that used in other processor architectures.

enable (core)
The process of preparing a virtual processor for operation, which will normally complete at the next system or power-on reset.

enabled (core)
A virtual processor that is in operation (participating in cache coherency, but not executing instructions unless it is also running). See also disabled and running.

even parity
The mode of parity checking in which each combination of data bits plus a parity bit contains an even number of ‘1’ bits.

exception
A condition that makes it impossible for the processor to continue executing the current instruction stream. Some exceptions (for example, floating-point exceptions; see FSR.tem) may be masked (that is, trap generation disabled) so that the decision on whether or not to apply special processing can be deferred and made by software at a later time. See also trap.

explicit ASI
An ASI that that is provided by a load, store, or load-store alternate instruction (either from its imm_asi field or from the ASI register).

extended word
An 8-byte datum, nominally containing integer data. Note: The definition of this term is architecture dependent and may differ from that used in other processor architectures.

fccn
One of the floating-point condition code fields fcc0, fcc1, fcc2, or fcc3.

fiber
Refers to an execution pipeline. It is a loose term for the basic collection of hardware needed to execute instructions. A fiber may be used by one or more strands to execute instructions from one or more threads. See also physical core, processor, strand, thread, and virtual processor.

floating-point exception
An exception that occurs during the execution of a floating-point operate (FPop) instruction. The exceptions are unfinished_FPop, unimplemented_FPop, sequence_error, hardware_error, invalid_fp_register, or IEEE_754_exception.

F register
A floating-point register. SPARC V9 includes single-, double-, and quad-precision F registers.

IEEE 754
IEEE Standard 754-1985, the IEEE Standard for Binary Floating-Point Arithmetic.

IEEE-754 exception
A floating-point exception, as specified by IEEE Std 754-1985. Listed within this specification as IEEE_754_exception.

floating-point operate (FPop) instructions
Instructions that perform floating-point calculations, as defined in Floating-Point Operate (FPop) Instructions on page 144. FPop instructions do not include FBfcc instructions, loads and stores between memory and the F registers, or non-floating-point operations that read or write F registers.

floating-point trap type
The specific type of a floating-point exception, encoded in the FSR.ftt field. floating-point unit A processing unit that contains the floating-point registers and performs floating-point operations, as defined by this specification.

FPop
See floating-point operate (FPop) instructions.

FPRS
Floating-Point Register State register.

FSR
Floating-Point Status register.

GL
Global Level register.

GSR
General Status register.

FPU
Floating-point unit.

halfword
A 2-byte datum. Note: The definition of this term is architecture dependent and may differ from that used in other processor architectures.

hyperprivileged (software)
Software executing while the processor is in hyperprivileged state.

hyperprivileged (state) The highest processor privilege state (defined by HPSTATE.hpriv = 1), in which all processor features are accessible.

-- DwayneLee - 23 Feb 2007