Core Tunning

Changing the Number of Cores

Changing the Number of FPUs

Simplifiying the ISA

Changing Cache Sizes

Chaging the Register Window

Architectural Simulation

Architectural simulators are useful tools for evaluating future OpenSPARC processors. This sections explains how to use SESC to model OpenSPARC.

Running SAM

Generating RST Traces with SAM

Modeling OpenSPARC with SESC

SESC is a cycle accurate architectural simulator. It models a very wide set of architectures: single processors, CMPs, PIMs, and thread level speculation. It is available under GPL license from sourceforge.

SESC can work with multiple ISAs: MIPS, PowerPC? , and SPARC. To model OpenSPARC, we use the SPARC support. This could be done reading traces generated by SAM or with the execution-driven model from QEMU.

Trace-Driven Simulation

Execution-Driven Simulation

-- JoseRenau? - 17 Jun 2006